Phase detection circuits are increasingly being implemented in digital form, as is the trend for circuits in general. Digital implementations offer numerous benefits over analog alternatives, not the least of which are lower power consumption and reduced noise susceptibility. Both power and noise are primary considerations when selecting an all-digital phase-locked loop (ADPLL) implementation over an at least partially analog implementation. Low power and low noise demands are often found in communication systems, as are phase-locked loops (PLLs).
An all-digital implementation does not, however, relieve all constraints on PLL design. Many ADPLLs rely on a TDC to perform phase detection. TDCs produce a digital output, which is highly advantageous for processing digital signals. Unfortunately, they also produce significant noise. More specifically, the quantization a TDC necessarily performs introduces noise inversely proportional to the TDC's time resolution, which, in turn, is derived from gate-level delay times. A variety of improvements to the TDC resolution have been made, including the addition of Vernier delay chains and the evolution of two-stage TDCs. These improvements often yield resolution at the expense of space (footprint) and power, by adding power-consuming components and negating at least some of the benefit of being digital.
Further efforts have been made to reduce the “window” in which the TDC operates, otherwise known as the “measurement window.” Conventionally, the TDC operates for the duration of a pulse of a reference signal. In a PLL, the reference signal is the source on which the PLL is attempting to lock. As a reference pulse propagates through the TDC, components are active and power is consumed. Higher resolution TDCs often add to the number of components. Efforts have focused on reducing the measurement window from the conventional reference pulse width without introducing noise and degrading resolution. One approach is to trim down the window size over time. The initial window may be the conventional reference pulse width, which is then reduced over time as long as precision is maintained. If precision falls off, the window can be enlarged to reacquire the reference phase.
Other developments have yielded designs effectively dictating a time window in which the TDC operates. One such approach is to trim the reference pulse by a programmable time delay. This approach provides an avenue to tune the time delay statically, through component selection, or dynamically. The trimmed reference pulse propagates through the TDC for as long as the programmable delay allows, depending on the desired noise and resolution performance. Alternatively, the inherent delay within the TDC itself can be used to define the window. Certain TDC designs include a delay chain of some sort as an element of the quantization process. In those TDCs, the window can be defined as the time it takes the reference pulse to propagate through the delay chain. These developments were ultimately valuable pursuits, yielding TDC designs that can maintain precision with a reduced measurement window. The reduced measurement window limits the power consumption of the TDC and the overall power consumption of the host integrated circuit, such as an ADPLL.